24.3.8 Queue Threshold Control Register

Name: I3CxQUETHLDCON
Offset: 0x7A901C

Bit 3130292827262524 
 IBISTATHLD[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000001 
Bit 2322212019181716 
 IBIDATTHLD[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 RESPBUFTHLD[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000001 
Bit 76543210 
 CMDEBTHLD[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 31:24 – IBISTATHLD[7:0] In-Band Interrupt Status Threshold Value bits

This field controls the number of IBI status entries (or greater) in the IBI queue that trigger the IBITHLDSTA interrupt. The valid range is 0 to 7. A value of 0 sets the threshold for 1 entry, and a value of N sets the threshold for N+1 entries. Each IBI status entry can represent the complete (IBI payload byte size ≤ 4* IBIDATTHLD) IBI payload or a segment (IBI payload byte size > 4* IBIDATTHLD) of the IBI payload.

Bits 23:16 – IBIDATTHLD[7:0] IBI Data Threshold Value bits

This field represents the IBI data segment size in DWORD (4 bytes). The minimum supported segment size is 1 (4 bytes), and the maximum supported size is 31. The IBIDATTHLD field enables the slicing of the incoming IBI data and generates individual status, promoting the cut-through operation in reading out the IBI data.

Bits 15:8 – RESPBUFTHLD[7:0] Response Buffer Threshold Value bits

Controls the number of entries (or greater) in the Response Queue that trigger the RESPQSTA interrupt. The valid range is 0 to 3. The software programs only valid values. A value of 0 sets the threshold for 1 entry, and a value of N sets the threshold for N+1 entries.

Bits 7:0 – CMDEBTHLD[7:0] Command Buffer Empty Threshold Value bits

Controls the number of empty locations (or greater) in the Command Queue that trigger the CMDQSTA interrupt. The valid range is 0 to 7. A value of N ranging from 1 to 7 sets the threshold to N empty locations, and a value of 0 sets the threshold to indicate that the queue is completely empty.