24.3.45 Target Mode Release SDA Timing Register

Name: I3C1RELSDATIM
Offset: 0x7A90EC

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     RELSDATIM[19:16] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 15141312111098 
 RELSDATIM[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 01001111 
Bit 76543210 
 RELSDATIM[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00100000 

Bits 19:0 – RELSDATIM[19:0] Release SDA Count Value bits

This field is used in the Target mode of operation to release the SDA line if SCL does not change for a prescribed amount of time programmed in this register (RELSDATIM * peripheral clock period).