24.3.29 Target Mode Maximum Data Speed Register

Name: I3CxTGTDATSPD
Offset: 0x7A9084

Bit 3130292827262524 
      SETACTSTATEACTSTATE[1:0] 
Access R/WR/WR/W 
Reset 000 
Bit 2322212019181716 
 Reserved[3:0]STPPRMITCLKDATTIME[2:0] 
Access RRRRR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
      MAXRDSPD[2:0] 
Access R/WR/WR/W 
Reset 000 
Bit 76543210 
     DEFBYTMAXWRSPD[2:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bit 26 – SETACTSTATE

ValueDescription
1 The Active Controller should set the bus to the activity state indicated by bits 25:24 before handing off to this device.
0 The Active Controller should not set the bus to any activity state before handing off to this device.

Bits 25:24 – ACTSTATE[1:0]

ValueDescription
11 Acts according to Activity State 3.
10 Acts according to Activity State 2.
01 Acts according to Activity State 1.
00 Acts according to Activity State 0.

Bits 23:20 – Reserved[3:0]

Bit 19 – STPPRMIT

Specifies the stop support between write and read.
ValueDescription
1 The Target permits the write and read to be split by a stop.
0 Stop will cancel the read.

Bits 18:16 – CLKDATTIME[2:0]

Specifies the clock-to-data turnaround time of the Target.
ValueDescription
0111-0101 Reserved
0100 12 ns
0011 11 ns
0010 10 ns
0001 9 ns
0000 8 ns

Bits 10:8 – MAXRDSPD[2:0]

Specifies the maximum sustained data rate for non-CCC messages sent by the Target to the Controller device.
ValueDescription
0111-0101 Reserved
0100 2 MHz
0011 4 MHz
0010 6 MHz
0001 8 MHz
0000 12.5 MHz

Bit 3 – DEFBYT

Specifies the defining byte support of GETMXDS CCC.
ValueDescription
1 Supports the defining byte.
0 Does not support the defining byte.

Bits 2:0 – MAXWRSPD[2:0]

Specifies the maximum sustained data rate for non-CCC messages sent by the Controller device to the Target.
ValueDescription
0111-0101 Reserved
0100 2 MHz
0011 4 MHz
0010 6 MHz
0001 8 MHz
0000 12.5 MHz