24.3.1 Device Control Register
Note:
- In Target mode, the I3C operation is enabled only after providing SCL clocks to bring it out of Reset. This can be achieved by scheduling any transfer (placeholder transfer) ending in a STOP before initiating valid transfers. The placeholder transfer is ignored by the Target. Once enabled, the module responds to transfers on the bus only after it observes the Bus Available condition for I3CxBUSTIM[BUSAVAILTIM] * I3CxCTRL[IDLECNT] counts of the peripheral clock period.
- The Controller gets disabled after the commands in the command queue (if any) are executed, and the Controller is in the IDLE state.
| Name: | I3CxCTRL |
| Offset: | 0x7A9000 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ON | RESUME | ABORT | DMAEN | ADPTV | PEC | IDLECNT[1:0] | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| HOTJOIN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| I2CTGT | IBA | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 31 – ON I3C Enable bit
| Value | Description |
|---|---|
| 1 | Enables the I3C operation(1). |
| 0 | Disables the I3C operation(2). |
Bit 30 – RESUME I3C Module Resume bit
| Value | Description |
|---|---|
| 1 | I3C module operation resume enable. |
| 0 | I3C module resume operation complete. Auto-cleared once the module resumes. |
Bit 29 – ABORT I3C Module Abort bit (Controller mode only)
| Value | Description |
|---|---|
| 1 | Abort ongoing transaction. The Controller issues the STOP condition after the complete data byte is transferred or received. |
| 0 | Abort completed, auto-cleared once the transfer is aborted. |
Bit 28 – DMAEN DMA Handshake Interface Enable bit
| Value | Description |
|---|---|
| 1 |
Enables the DMA handshake control to interact with the DMA. |
| 0 |
The DMA handshake control has no significance. |
Bit 27 – ADPTV Adaptive mode bit (Target mode only)
| Value | Description |
|---|---|
| 1 | Hot-Join request is initiated only after it has switched to I3C mode of operation. |
| 0 | Initiates a Hot-Join always. |
Bit 26 – PEC PEC Enable bit
| Value | Description |
|---|---|
| 1 | PEC support is enabled. |
| 0 | PEC support is not enabled. |
Bits 25:24 – IDLECNT[1:0] Idle Count Multiplier bits (Target mode only)
| Value | Description |
|---|---|
| 11 | I3CxBUSTIM[BUSAVAILTIM] * 8 |
| 10 | I3CxBUSTIM[BUSAVAILTIM] *4 |
| 01 | I3CxBUSTIM[BUSAVAILTIM] * 2 |
| 00 | I3CxBUSTIM[BUSAVAILTIM] * 1 |
Bit 8 – HOTJOIN Hot-Join ACK/NACK Control bit (Controller mode only)
| Value | Description |
|---|---|
| 1 | NACK and send broadcast CCC to disable Hot-Join. |
| 0 | ACK the Hot-Join request. |
Bit 7 – I2CTGT (Controller mode only)
| Value | Description |
|---|---|
| 1 | I2C Target present. |
| 0 |
I2C Target not present. |
Bit 0 – IBA I3C Broadcast Address Include bit (Controller mode only)
| Value | Description |
|---|---|
| 1 | I3C Broadcast Address is included for private transfers. |
| 0 | I3C Broadcast Address is not included for private transfers. |
