24.3.31 Target Interrupt Request Data Register

Name: I3CxTGTSIRDAT
Offset: 0x7A9094

This register, I3CxCLTSIRDAT, containing four bytes of SIR Data, will be in effect only when I3CxCLTINT [SIRCTRL] is programmed to 0000. SIR DATA will be passed after the MDB.

Bit 3130292827262524 
 SIRBYT3[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
 SIRBYT2[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
 SIRBYT1[0]        
Access R/W 
Reset 0 
Bit 76543210 
 SIRBYT0[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 31:24 – SIRBYT3[7:0] Target Interrupt Request Data Byte 3 bits

Bits 23:16 – SIRBYT2[7:0] Target Interrupt Request Data Byte 2 bits

Bits 22:15 – SIRBYT1[7:0] Target Interrupt Request Data Byte 1 bits

Bits 7:0 – SIRBYT0[7:0] Target Interrupt Request Data Byte 1 bits