24.3.19 Present State Register
Note:
- This bit is set when all the queues (Command, Response, IBI) and buffers (Transmit and Receive) are empty, along with the Controller State machine being in an Idle state.
- A software Reset will not have any effect on this field.
| Name: | I3CxSTATE |
| Offset: | 0x7A9054 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| IDLESTATE | CMDTID[3:0] | ||||||||
| Access | R | R | R | R | R | ||||
| Reset | 1 | 0 | 0 | 0 | 0 | ||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CMTFRSTAT[5:0] | |||||||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| CMTFRTYP[5:0] | |||||||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CURRCNTRL | SDALEVEL | SCLLEVEL | |||||||
| Access | R | R | R | ||||||
| Reset | 1 | 0 | 0 |
Bit 28 – IDLESTATE Controller Mode Idle bit
| Value | Description |
|---|---|
| 1 | Controller is in IDLE State(1) . |
| 0 | Controller is not in IDLE State. |
Bits 27:24 – CMDTID[3:0]
Bits 21:16 – CMTFRSTAT[5:0] Current Controller Transfer State Status (Controller mode only)
| Value | Description |
|---|---|
| 010011 | Halt state |
| 010010 | Clock Extension state |
| 010001 | HDR-DDR CRC Data Generation/Receive state |
| 010000 | In-Band Interrupt Auto-Disable state |
| 001111 | In-Band Interrupt (SIR) Read Data state |
| 001110 | Read Data Transfer state |
| 001101 | Write Data Transfer state |
| 001100 | HDR Command Generation state |
| 001011 | CCC Byte Generation state |
| 001000 | Target Address Generation State |
| 000111 | Dynamic Address Assignment state |
| 000110 | Broadcast Read Address Header(7'h7E,R) Generation state |
| 000101 | Broadcast Write Address Header(7'h7E,W) Generation state |
| 000100 | START Hold Generation for the Target Initiated START state |
| 000011 | Stop Generation state |
| 000010 | Restart Generation state |
| 000001 | Start Generation state |
| 000000 | Controller is Idle |
Bits 13:8 – CMTFRTYP[5:0] Current Transfer Type Status bits
| Value | Description |
|---|---|
|
In Controller mode of operation: |
|
| 010001 | Reserved |
| 010000 | Reserved |
| 001111 | Halt state (Controller is in Halt state, waiting for the application to resume through DEVICE_CTRL register.) |
| 001110 | Servicing In-Band Interrupt Transfer |
| 001101 | Private HDR Double-Data Rate(DDR) read transfer |
| 001100 | Private HDR Double-Data Rate(DDR) write transfer |
| 001011-001010 | Reserved |
| 001001 | Private I2C SDR read transfer |
| 001000 | Private I2C SDR write transfer |
| 000111 | Private I3C SDR read transfer |
| 000110 | Private I3C SDR write transfer |
| 000101 | SETDASA Address assignment transfer |
| 000100 | ENTDAA Address assignment transfer |
| 000011 | Directed CCC read transfer |
| 000010 | Directed CCC write transfer |
| 000001 | Broadcast CCC write transfer |
| 000000 | IDLE (Controller is in Idle state, waiting for commands from application or Target initiated In-Band Interrupt) |
| In Target mode of operation: | |
| 000110 | Target controller in Halt state, waiting for resume from application. |
| 000101 | Controller read transfer ongoing. |
| 000100 | Read Data Prefetch state |
| 000011 | Controller write transfer ongoing. |
| 0000010 | IBI Transfer state |
| 000001 | Hot-Join Transfer state |
| 000000 | IDLE (Controller is in Idle state.) |
Bit 2 – CURRCNTRL Current Controller State Status bit(2)
| Value | Description |
|---|---|
| 1 | Controller is current Controller. |
| 0 | Controller is not current Controller. |