24.3.166 Device Address Table Location of Device(n) Register


Bit	31	30	29	28	27	26	25	24
	DEVICE	DEVNACKRTRYCNT[1:0]
Access	R/W	R/W	R/W
Reset	0	0	0


Bit	23	22	21	20	19	18	17	16
	DEVDYNADDR[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	TS	MRREJ	SIRREJ	IBIWITHDAT	IBIWITHDAT		DDRERLYTERMNCRCIND	DDRWRERLYTERMNEN
Access	R/W	R/W	R/W	R/W	R/W		R/W	R/W
Reset	0	0	0	0	0		0	0


Bit	7	6	5	4	3	2	1	0
	DDRWRACKNACKEN	STATICADDR[6:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bit 31 – DEVICE Type of Device bit

Value	Description
1	I²C
0	I³C

Bits 30:29 – DEVNACKRTRYCNT[1:0]

This field is used to set the Device NACK Retry count for a particular device.

Bits 23:16 – DEVDYNADDR[7:0] Device Dynamic Address with Parity bits

This field consists of a Dynamic Address and a parity bit. The LSB bits [22:16] should consist of the Dynamic Address field, which indicates the address to be assigned to the winning I³C device when using the ENTDAA command. The MSB[23] bit is the odd parity of the 7-bit Dynamic Address used for ENTDAA address assignment (~XOR(DEVDYNADDR [22:16])).

Bit 15 – TS Marker for Timestamping IBI for Specific Device bit

Bit 14 – MRREJ

In-Band Controller Request Reject field is used to control, per device, whether to accept Controller requests from devices.

Value	Description
1	NACK the Controller request and send auto-disable CCC.
0	ACK the Controller request.

Bit 13 – SIRREJ

In-Band Target Interrupt Request Reject field is used to control, per device, whether to accept Target interrupt requests from devices.

Value	Description
1	NACK the SIR and send auto-disable CCC.
0	ACK the SIR.

Bit 12 – IBIWITHDAT

One or more mandatory data bytes follow the accepted IBI from the device. Data byte continuation is indicated by the T-bit.

Value	Description
1	IBI with one or more mandatory bytes.
0	IBI without a mandatory byte.

Bit 11 – IBIWITHDAT

Packet Error Check enabled for accepted IBI from the device. PEC byte is appended at the end of IBI data from the device. This bit controls whether a PEC check should be performed for IBI data from the device. This bit also controls whether the PEC byte has to be sent for auto-disable CCC when the Controller NACKs the IBI.

Value	Description
1	Packet Error Check enabled for IBI.
0	Packet Error Check disabled for IBI.

Bit 9 – DDRERLYTERMNCRCIND

Enable DDR transfer Early Termination CRC Word Indicator bit

Bit 8 – DDRWRERLYTERMNEN

Enable DDR WRITE Early Termination Request bit

Bit 7 – DDRWRACKNACKEN

Enable ACK/NACK Capability for DDR WRITE Command bit

Name:	I3CxDEVADDRTAB6LOC1
Offset:	0x7A9394