24.3.12 Target Mode Event Status Register

Note:
  1. If this field is not set to 0 by the Target application, it can be set or cleared by the I3C Controller through ENEC or DISEC CCCs. Once disabled by software, CCCs do not have any effect on this field.
  2. Usually, this bit is set or cleared by the I3C Controller through ENEC or DISEC CCC.
Name: I3CxTGTESTA
Offset: 0x7A9038

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 MWLSTAMRLSTAACTSTA[1:0]HJINTEN MRINTEN  
Access RR/W1CRRR/WR/W 
Reset 000011 

Bit 7 – MWLSTA MWL Updated Status bit

This bit is set when SETMWL CCC is received by the Target. This status can be cleared by writing 1'b1 to this field after reading the updated MWL.

Bit 6 – MRLSTA MRL Updated Status bit

This bit is set when the SETMRL CCC is received by the Target. This status can be cleared by writing 1'b1 to this field after reading the updated MRL.

Bits 5:4 – ACTSTA[1:0] Activity State Status bits

ValueDescription
11 ENTAS3
10 ENTAS2
01 ENTAS1
00 ENTAS0

Bit 3 – HJINTEN  Hot-Join Interrupt Enable bit(1)

ValueDescription
1 Enable Hot-Join capability.
0 Disable Hot-Join capability.

Bit 1 – MRINTEN  Commander Request Enable bit(2)

ValueDescription
1 Enable Controller request capability.
0 Disable Controller request capability.

Bit 1 – SIRINTEN  Target Interrupt Request Enable bit(2)

ValueDescription
1 Enable Target interrupt request capability.
0 Disable Target interrupt request capability.