24.3.3 Hardware Capability Register

Name: I3CxHWCAP
Offset: 0x7A9008

This register reflects the configured capabilities of the module.

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 HDRBN VIRTGTGRPADDRIBICAPHJCAPDMACAPHDRCLKPR[5] 
Access R/WRRRRRR 
Reset 0111110 
Bit 15141312111098 
 HDRCLKPR[4:0]CLOCKPERIOD[5:3] 
Access RRRRRRRR 
Reset 01000010 
Bit 76543210 
 CLOCKPERIOD[2:0]HDRTSHDRDDRDEVROLE[2:0] 
Access RRRRRRRR 
Reset 10101011 

Bit 23 – HDRBN

ValueDescription
1 HDR-BT is supported.
0 HDR-BT is not supported.

Bit 21 – VIRTGT

ValueDescription
1 Virtual Target is supported.
0 Virtual Target is not supported.

Bit 20 – GRPADDR

ValueDescription
1 Group Address is supported.
0 Group Address is not supported.

Bit 19 – IBICAP

ValueDescription
1 IBI is capable.
0 IBI is not capable.

Bit 18 – HJCAP

ValueDescription
1 Hot-Join is capable.
0 Hot-Join is not capable.

Bit 17 – DMACAP

ValueDescription
1 DMA handshake interface is supported.
0 DMA handshake interface is not supported.

Bits 16:11 – HDRCLKPR[5:0]

Reflects the HDR clock period.

Bits 10:5 – CLOCKPERIOD[5:0]

Reflects clock period.

Bit 4 – HDRTS

ValueDescription
1 HDR-TS is supported.
0 HDR-TS is not supported.

Bit 3 – HDRDDR

ValueDescription
1 HDR-DDR is supported.
0 HDR-DDR is not supported.

Bits 2:0 – DEVROLE[2:0]

Specifies the configured role of module.
ValueDescription
100 Target only
011 Secondary Controller
001 Controller only