24.3.41 Target Mode Bus Free Avail Timing Register
| Name: | I3CxBUSTIM |
| Offset: | 0x7A90D4 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| BUSAVAILTIM[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| BUSAVAILTIM[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BUSFREETIM[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| BUSFREETIM[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | |
Bits 31:16 – BUSAVAILTIM[15:0] Bus Available Count Value bits
Bits 15:0 – BUSFREETIM[15:0] I3C Bus Free Count Value bits
In a pure bus system, this field represents the tCAS parameter. In a mixed bus system, this field is expected to be programmed to tLOW of I2C Timing.