24.3.13 Interrupt Status Register

Note:

This interrupt is provided for the user/application (current active Controller) to decide whether the new active Controller has taken over the ownership after the bus handover was completed successfully to move to Target mode. This interrupt is also used to reset the Reset action configured by the RSTACT CCC.

Name:	I3CxINTSTA
Offset:	0x7A903C


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
			EXTCMDTXTHLDSTA	EXTCMDSTA	SDARELSTA	GRPADDRSTA	TRSTPATSTA	STARTSTA
Access			R	R	R/W1C	R/W1C	R/W1C	R/W1C
Reset			0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	BUSRSTSTA		BUSOWNSTA	IBIUPDSTA	READREQSTA	DEFTGTSTA	TRANSERRSTA	DYNADDRSTA
Access	R/W1C		R/W1C	R/W1C	R/W1C	R/W1C	R/W1C	R/W1C
Reset	0		0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
		CCCUPDSTA	TRANSABTSTA	RESPQSTA	CMDQSTA	IBITHLDSTA	RXTHLDSTA	TXTHLDSTA
Access		R/W1C	R/W1C	R	R	R	R	R
Reset		0	0	0	0	0	0	0

Bit 21 – EXTCMDTXTHLDSTA I3CxEXTCMDy Transmit Buffer Threshold Status bit (Target mode only)

Value	Description
1	The number of empty locations in any I3CxEXTCMDy Transmit Buffer is greater than or equal to the threshold value specified by I3CxECRTCON [CMDTXBUFTHLD].
0	Cleared automatically when the number of empty locations in all the I3CxEXTCMDy Transmit Buffers is less than the threshold value specified.

Bit 20 – EXTCMDSTA I3CxEXTCMDy Has Finished Status bit (Target mode only)

Value	Description
1	Read transfer has finished in the I3CxEXTCMDy.
0	Cleared automatically when the register I3CxECMDVLDSTA is read.

Bit 19 – SDARELSTA SDA Released from Stuck State Status bit (Target mode only)

This interrupt is generated if the SCL was not changed for the prescribed amount of time defined by the I3CxRELSDATIM register. This bit can be cleared by writing 1'b1.

Bit 18 – GRPADDRSTA Group Address Assigned Status bit (Target mode only)

This interrupt is generated if one of the device's Group Addresses is assigned through SETGRPA CCC or reset through RSTGRPA CCC. This bit can be cleared by writing 1'b1.

Bit 17 – TRSTPATSTA Target Reset Pattern Detection Interrupt bit (Target mode only)

This interrupt is generated when the Target Reset pattern is detected.

Bit 16 – STARTSTA START Detection Interrupt bit (Target mode only)

This field indicates START detected in Target mode of operation. This bit can be cleared by writing 1'b1.⁽¹⁾

Bit 15 – BUSRSTSTA Bus Reset Pattern Generation Done Status bit

This interrupt is generated when the requested Bus Reset pattern generation is completed. This bit can be cleared by writing '1b1'.

Bit 13 – BUSOWNSTA

This interrupt is set when the role of the Controller changes from being a Controller to a Target, or vice versa. This bit can be cleared by writing 1'b1.

Bit 12 – IBIUPDSTA IBI Status is Updated bit (Target mode only)

Indicates that the IBI request initiated through the SIR request register is addressed and the status is updated.

Bit 11 – READREQSTA Read Request Received bit (Target mode only)

Read request received from the current Controller when CMDQ is empty. This bit can be cleared by writing 1'b1.

Bit 10 – DEFTGTSTA Define Target CCC Received Status bit

This interrupt is generated if the DEFSLV CCC is received. This bit can be cleared by writing 1'b1.

Bit 9 – TRANSERRSTA Transfer Error Status bit

Bit 8 – DYNADDRSTA Dynamic Address Assigned Status bit (Target mode only)

This interrupt is generated if the device's Dynamic Address is assigned through SETDASA, SETAASA, SETNEWDA or ENTDAA CCC. This bit can be cleared by writing 1'b1.

Bit 6 – CCCUPDSTA CCC Table Updated Status bit (Target mode only)

This interrupt is generated if any of the CCC registers are updated by the I³C Controller through CCC commands. This interrupt can be cleared by writing 1'b1.

Bit 5 – TRANSABTSTA Transfer Abort Status bit (Controller mode only)

This interrupt is generated if the transfer is aborted. This interrupt can be cleared by writing 1'b1.

Bit 4 – RESPQSTA Response Queue Ready Status bit

This interrupt is generated when the number of entries in the Response Queue is greater than or equal to the threshold value specified by the I3CxQUETHLDCON[RESPBUFTHLD] register. This interrupt is cleared automatically when the number of entries in the Response Buffer is less than the threshold value specified.

Bit 3 – CMDQSTA Command Queue Ready bit

This interrupt is generated when the number of empty locations in the Command Queue is greater than or equal to the threshold value specified by the I3CxQUETHLDCON[CMDEBTHLD] register. This interrupt is cleared automatically when the number of empty locations in the Command Buffer is less than the specified threshold value.

Bit 2 – IBITHLDSTA IBI Buffer Threshold Status bit

This interrupt is generated when the number of entries in the IBI Buffer is greater than or equal to the threshold value specified by the I3CxQUETHLDCON[IBISTATHLD] register. This interrupt is cleared automatically when the number of entries in the IBI Buffer is less than the specified threshold value.

Bit 1 – RXTHLDSTA Receive Buffer Threshold Status bit

This interrupt is generated when the number of entries in the Receive Buffer is greater than or equal to the threshold value specified by the I3CxBUFTHLD [RXBUF] register. This interrupt is cleared automatically when the number of entries in the Receive Buffer is less than the threshold value specified.

Bit 0 – TXTHLDSTA Transmit Buffer Threshold Status bit

This interrupt is generated when the number of empty locations in the Transmit Buffer is greater than or equal to the threshold value specified by the I3CxBUFTHLD [TXBUF] register. This interrupt is cleared automatically when the number of empty locations in the Transmit Buffer is less than the specified threshold value.