24.3.36 Controller Mode SCL
I2C Fast Mode Timing Register
Note:
The count value takes the
number of peripheral clocks to maintain the I/O SCL High/Low Period
timing.
Name:
I3CxI2CFMTIM
Offset:
0x7A90BC
Bit
31
30
29
28
27
26
25
24
FMHCNT[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
23
22
21
20
19
18
17
16
FMHCNT[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
1
0
0
0
0
Bit
15
14
13
12
11
10
9
8
FMLCNT[15:8]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
FMLCNT[7:0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
0
0
0
1
0
0
0
0
Bits 31:16 – FMHCNT[15:0]
I2C Fast Mode High Count bits
The SCL open-drain
high count timing for I2C fast mode transfers.
Bits 15:0 – FMLCNT[15:0]
I2C Fast Mode Low Count bits
The SCL open-drain low count
timing for I2C fast mode transfers.
DS70005629B
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