24.3.38 Controller Mode SCL Extended Low Count Timing Register

Note: This register sets the extended low periods for the I3C transfers to allow the low data rates of the Target devices as specified in the GETMXDS CCC.
Name: I3CxSCLELCNT
Offset: 0x7A90C8

Bit 3130292827262524 
 LCNT4[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00100000 
Bit 2322212019181716 
 LCNT3[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00100000 
Bit 15141312111098 
 LCNT2[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00100000 
Bit 76543210 
 LCNT1[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00100000 

Bits 31:24 – LCNT4[7:0]  I3C Extended Low Count Register 4 bits

SDR4 uses this register field for data transfer.

Bits 23:16 – LCNT3[7:0]  I3C Extended Low Count Register 3 bits

SDR3 uses this register field for data transfer.

Bits 15:8 – LCNT2[7:0]  I3C Extended Low Count Register 2 bits

SDR2 uses this register field for data transfer.

Bits 7:0 – LCNT1[7:0]  I3C Extended Low Count Register 1 bits

SDR1 uses this register field for data transfer.