24.3.39 Controller Mode SCL Termination Bit Low Count Timing Register

Note: This register is used to extend the SCL Low period for the Read Termination bit. This register is applicable only in Controller mode.
Name: I3CxSCLETLCNT
Offset: 0x7A90CC

Bit 3130292827262524 
 STOPHLDCNT[3:0]     
Access R/WR/WR/WR/W 
Reset 0001 
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
     TERMNLCNT[3:0] 
Access R/WR/WR/WR/W 
Reset 0000 

Bits 31:28 – STOPHLDCNT[3:0] STOP HOLD Count bits

Stop Hold Count in terms of the peripheral clock, which is used for the generation of Stop Hold in Controller mode.

Bits 3:0 – TERMNLCNT[3:0] I3C Read Termination Bit Low Count bits

Extended I3C Read Termination Bit low count for I3C read transfers. Effective Termination-Bit low period is derived based on the SDR speed as shown below:
  • SDR0 speed: PPLCNT + TERMNLCNT
  • SDR1 speed: LCNT1 + TERMNLCNT
  • SDR2 speed: LCNT2 + TERMNLCNT
  • SDR3 speed: LCNT3 + TERMNLCNT
  • SDR4 speed: LCNT4 + TERMNLCNT