24.3.14 Interrupt Status Enable
Register
| Name: | I3CxINTSTACON |
| Offset: | 0x7A9040 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | EXTCMDTXTHLDSTAEN | EXTCMDSTAEN | SDARELSTAEN | GRPADDRSTAEN | TRSTPATSTAEN | STARTSTAEN | |
| Access | | | R | R | R/W | R/W | R/W | R/W | |
| Reset | | | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | BUSRSTSTAEN | | BUSOWNSTAEN | IBIUPDSTAEN | READREQSTAEN | DEFTGTSTAEN | TRANSERRSTAEN | DYNADDRSTAEN | |
| Access | R/W | | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | CCCUPDSTAEN | TRANSABTSTAEN | RESPQSTAEN | CMDQSTAEN | IBITHLDSTAEN | RXTHLDSTAEN | TXTHLDSTAEN | |
| Access | | R/W | R/W | R/W | R/W | R | R/W | R/W | |
| Reset | | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 21 – EXTCMDTXTHLDSTAEN I3CxEXTCMDy
Transmit Buffer Threshold Status Enable bit
This field is used
in Target mode of operation.
Bit 20 – EXTCMDSTAEN I3CxEXTCMDy has
Finished Status Enable bit
This field is used in Target
mode of operation.
Bit 19 – SDARELSTAEN SDA Released from
Stuck State Status Enable bit
This field is used in Target
mode of operation.
Bit 18 – GRPADDRSTAEN Group Address
Assigned Status Enable bit
This field is used only in
Target mode of operation.
Bit 17 – TRSTPATSTAEN Target Reset
Pattern Detection Status Enable bit
This field is used only in
Target mode of operation.
Bit 16 – STARTSTAEN START Detection
Status Enable bit
This field is used only in
Target mode of operation.
Bit 15 – BUSRSTSTAEN Bus Reset Pattern
Generation Done Status Enable bit
This field is used only in
Controller mode of operation.
Bit 13 – BUSOWNSTAEN Bus Owner Updated
Status Enable bit
Bit 12 – IBIUPDSTAEN IBI Updated Status
Enable bit
This field is used in Target
mode of operation.
Bit 11 – READREQSTAEN Read Request
Received Status Enable bit
This field is used in Target
mode of operation.
Bit 10 – DEFTGTSTAEN Define Target CCC
Received Status Enable bit
Bit 9 – TRANSERRSTAEN Transfer Error
Status Enable bit
Bit 8 – DYNADDRSTAEN Dynamic Address
Assigned Status Enable bit
This field is used in Target
mode of operation.
Bit 6 – CCCUPDSTAEN CCC Table Updated
Status Enable bit
This field is used in Target
mode of operation.
Bit 5 – TRANSABTSTAEN Transfer Abort
Status Enable bit
This field is used in
Controller mode of operation.
Bit 4 – RESPQSTAEN Response Queue
Ready Status Enable bit
Bit 3 – CMDQSTAEN Command Queue Ready
Status Enable bit
This field is used in
Controller mode of operation.
Bit 2 – IBITHLDSTAEN IBI Buffer
Threshold Status Enable bit
This field is used in
Controller mode of operation.
Bit 1 – RXTHLDSTAEN Receive Buffer
Threshold Status Enable bit
Bit 0 – TXTHLDSTAEN Transmit Buffer
Threshold Status Enable bit
