24.3.33 Device Control Extended Register
| Name: | I3CxCTRLEXT |
| Offset: | 0x7A90B0 |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DPSLPCAP | REQACKCTRL | DEVOPMOD[1:0] | |||||||
| Access | R/W | R/W | R | R | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bit 4 – DPSLPCAP Deep Sleep Capability of the Secondary Controller Device bit
| Value | Description |
|---|---|
| 1 | Module may enter a deep sleep state during which it may miss some Broadcast DEFTGTS and DEFGRPA CCCs sent by the Active Controller. It will require re-synchronization upon re-entering a normal operating state, before it can accept the Controller role with the GETACCCR CCC. |
| 0 | Module shall remain active and continue to monitor the I3C bus to listen for these Broadcast CCCs, and shall not enter a deep sleep state from which it must be re-synchronized by the Active Controller before it can accept the Controller role. |
Bit 3 – REQACKCTRL
| Value | Description |
|---|---|
| 1 | NACK GETACCMST CCC |
| 0 | ACK GETACCMST CCC |
Bits 1:0 – DEVOPMOD[1:0]
| Value | Description |
|---|---|
| 011-010 | Reserved |
| 001 | Target |
| 000 | Controller |