24.3.30 Target Mode Interrupt Request Register

Note:

This field should be programmed by the Target application to provide the data length for the payload data other than the MDB byte.
This field is only applicable when BCR[2] is set, indicating that SIR supports payload data.
When the conditions for entering a CE3 error are met (expiry of the application running timer and I3CxCLTINT [SIR] is not set to '0'), program this bit to recover from the CE3 error.
Upon receiving this bit, the target will move to Controller mode (update I3CXSTATE.CURRCNTRL bit to 1) and generate a START (also clear the I3CxCLTINT [SIR]) and continue by generating 7E followed by STOP.
If a NACK response is received for the MR, the Controller reattempts the MR upon detecting the next START condition from the Controller or after the Bus Available time. Once set, the application cannot clear this bit.
The target reattempts the SIR either upon detecting the next START condition from the Controller OR after the Bus Available Time if a NACK response is received for the SIR.
This feature is used in the CE3 error recovery flow. Once set, the application/software cannot clear this bit.

Name:	I3CxTGTINT
Offset:	0x7A908C


Bit	31	30	29	28	27	26	25	24
	SIRTGTINDX[3:0]
Access	R/W	R/W	R/W	R/W
Reset	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	SIRDATLEN[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	MDB[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CE3RECOV				MR	SIR[2:0]
Access	R/W				R/W	R/W	R/W	R/W
Reset	0				0	0	0	0

Bits 31:28 – SIRTGTINDX[3:0] SIR Target Index bits

Value	Description
1111-0101	Reserved
0100	Virtual Target 4
0011	Virtual Target 3
0010	Virtual Target 2
0001	Virtual Target 1
0000	Virtual Target 0

Bits 23:16 – SIRDATLEN[7:0] SIR Data Length bits^(1,2)

Bits 15:8 – MDB[7:0] Mandatory Data Byte bits⁽²⁾

Mandatory data byte that is required to be transmitted after the Controller Acknowledges the Target address during SIR transfer.

Bit 7 – CE3RECOV Recovery From CE3 Error bit^(3,4)

Value	Description
1	Recover from CE3 error.
0	Recovery complete, moved to Controller mode.

Bit 3 – MR Controller Request bit

Value	Description
1	Issue the MR on the I³C bus.
0	Clears when the current Controller accepts (ACK) or if the Controller is unable to issue the MR, then the Controller clears this bit automatically and updates the I3CxCLTIBIRESP [IBISTAT] field⁽⁵⁾.

Bit 1 – SIRCTRL Target Interrupt Request Control bit

Value	Description
1	Pull the SDA line low and release SDA after sampling SCL low (pulled by the Controller). Used for CE3 recovery during the Controller handover procedure.
0	Indicates the source of SIR data to be from the registers.

Bits 2:0 – SIR[2:0] Target Interrupt Request bits

Value	Description
1	Target attempts to issue the SIR on the I³C bus based on the SIRCTRL field.
0	If SIRCTRL = 00, the Target clears this bit automatically and updates the I3CxCLTIBIRESP [IBISTAT] field when either the current Controller accepts by generating (ACK) or if the Target controller is unable to issue the SIR (6). If SIRCTRL = 01, the Target controller clears this bit automatically after sampling the SCL Low (pulled by Controller) for the generated SDA low. The Target will release the SDA line upon sampling the SCL low⁽⁷⁾.

Value

Description

Target attempts to issue the SIR on the I³C bus based on the SIRCTRL field.

If SIRCTRL = 00, the Target clears this bit automatically and updates the I3CxCLTIBIRESP [IBISTAT] field when either the current Controller accepts by generating (ACK) or if the Target controller is unable to issue the SIR (6). If SIRCTRL = 01, the Target controller clears this bit automatically after sampling the SCL Low (pulled by Controller) for the generated SDA low. The Target will release the SDA line upon sampling the SCL low⁽⁷⁾.