17.2 UDDRC Operating Mode Status Register

Name: UDDRC_STAT
Offset: 0x004
Reset: 0x00000000
Property: Read-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
    SELFREF_CAM_NOT_EMPTY     
Access R 
Reset 0 
Bit 76543210 
   SELFREF_TYPE[1:0] OPERATING_MODE[2:0] 
Access RRRRR 
Reset 00000 

Bit 12 – SELFREF_CAM_NOT_EMPTY Self-refresh with CAMs not empty

Set to 1 when Self-refresh is entered but CAMs are not drained. Cleared after exiting Self-refresh.

Programming Mode: Static

Bits 5:4 – SELFREF_TYPE[1:0]

Flags if Self-refresh is entered and if it was under Automatic Self-refresh control only or not.

Programming Mode: Static

ValueDescription
00 SDRAM is not in Self-refresh. If retry is enabled by CRCPARCTRL1.crc_parity_retry_enable, this also indicates the SRE command is still in parity error window or retry is in progress.
11 SDRAM is in Self-refresh, which was caused by Automatic Self-refresh only. If retry is enabled, this ensures the SRE command is executed correctly without parity error.
10 SDRAM is in Self-refresh, which was not caused solely under Automatic Self-refresh control. It could have been caused by Hardware Low Power Interface and/or Software (PWRCTL.selfref_sw). If retry is enabled, this ensures the SRE command is executed correctly without parity error.
01 SDRAM is in Self-refresh, which was caused by PHY Host Request.

Bits 2:0 – OPERATING_MODE[2:0] Operating mode

This is 3-bit wide in configurations with LPDDR2/LPDDR3 support and 2-bit wide in all other configurations.

Programming Mode: Static

ValueDescription
Non-LPDDR2/LPDDR3 designs:
00 Init
01 Normal
10 Power-down
11 Self-refresh
LPDDR2/LPDDR3 designs:
000 Init
001 Normal
010 Power-down
011 Self-refresh
1XX Deep Power-down / Maximum Power Saving mode