17.73 UDDRC Temperature Derate Status Register
| Name: | UDDRC_DERATESTAT |
| Offset: | 0x3F0 |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DERATE_TEMP_LIMIT_INTR | |||||||||
| Access | R | ||||||||
| Reset | 0 |
Bit 0 – DERATE_TEMP_LIMIT_INTR
Derate temperature interrupt indicating LPDDR2/3 SDRAM temperature operating limit is exceeded.
This register field is set to 1 when the value read from MR4[2:0] is 3'b000 or 3'b111. Cleared by register DERATECTL.derate_temp_limit_intr_clr.
Programming Mode: Static