17.62 UDDRC Low Priority Read CAM Register 1
| Name: | UDDRC_PERFLPR1 |
| Offset: | 0x264 |
| Reset: | 0x0F00007F |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| LPR_XACT_RUN_LENGTH[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LPR_MAX_STARVE[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LPR_MAX_STARVE[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | |
Bits 31:24 – LPR_XACT_RUN_LENGTH[7:0]
Number of transactions that are serviced once the LPR queue goes critical is the
smaller of:
- (a) This number
- (b) Number of transactions available.
Unit: Transaction.
For performance only.
Programming Mode: Quasi-dynamic Group 3
Bits 15:0 – LPR_MAX_STARVE[15:0]
Number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not be disabled as it will cause excessive latencies.
For performance only.
Unit: DFI clock cycles.
Programming Mode: Quasi-dynamic Group 3