17.12 UDDRC Refresh Control Register 0


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	REFRESH_MARGIN[3:0]							REFRESH_TO_X1_X32[4]
Access	R/W	R/W	R/W	R/W				R/W
Reset	0	0	1	0				1


Bit	15	14	13	12	11	10	9	8
	REFRESH_TO_X1_X32[3:0]						REFRESH_BURST[5:4]
Access	R/W	R/W	R/W	R/W			R/W	R/W
Reset	0	0	0	0			0	0


Bit	7	6	5	4	3	2	1	0
	REFRESH_BURST[3:0]					PER_BANK_REFRESH
Access	R/W	R/W	R/W	R/W		R/W
Reset	0	0	0	0		0

Bits 23:20 – REFRESH_MARGIN[3:0]

Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2. It must always be less than internally used t_rfc_nom/32.

Note that internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32 * 32 if RFSHTMG.t_rfc_nom_x1_sel=0. If RFSHTMG.t_rfc_nom_x1_sel=1 (for LPDDR2/LPDDR3 per-bank refresh only), internally used t_rfc_nom is equal to RFSHTMG.t_rfc_nom_x1_x32. Note that, in LPDDR2/LPDDR3, internally used t_rfc_nom may be divided by four if derating is enabled (DERATEEN.derate_enable=1).

Unit: Multiples of 32 DFI clock cycles.

Programming mode: Dynamic - Refresh Related

Bits 16:12 – REFRESH_TO_X1_X32[4:0]

If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle for a period of time determined by this RFSHCTL0.refresh_to_x1_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is performed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are issued to the UDDRC.

For performance only.

Unit: DFI clock cycles or multiples of 32 DFI clock cycles, depending on RFSHTMG.t_rfc_nom_x1_sel.

Programming mode: Dynamic - Refresh Related

Bits 9:4 – REFRESH_BURST[5:0]

The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of refreshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshes.

For information on burst refresh feature refer to section 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf.

For DDR2/3, the refresh is always per-rank and not per-bank. The rank refresh can be accumulated over 8*tREFI cycles using the burst refresh feature.

In per-bank refresh mode of LPDDR2/LPDDR3 (RFSHCTL0.per_bank_refresh = 1), 64 refreshes can be postponed.

Programming mode: Dynamic - Refresh Related

Value	Description
0	Single refresh
1	Burst-of-2 refresh
7	Burst-of-8 refresh

Bit 2 – PER_BANK_REFRESH

Per-bank refresh allows traffic to flow to other banks. Per-bank refresh is not supported by all LPDDR2 devices but should be supported by all LPDDR3 devices. Present only in designs configured to support LPDDR2/LPDDR3.

Programming mode: Static

Value	Description
0	All-bank refresh
1	Per-bank refresh

Name:	UDDRC_RFSHCTL0
Offset:	0x050
Reset:	0x00210000
Property:	Read/Write