17.41 UDDRC DFI Low Power Configuration Register 0
| Name: | UDDRC_DFILPCFG0 |
| Offset: | 0x198 |
| Reset: | 0x07000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DFI_TLP_RESP[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 1 | 1 | 1 | ||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DFI_LP_WAKEUP_DPD[3:0] | DFI_LP_EN_DPD | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DFI_LP_WAKEUP_SR[3:0] | DFI_LP_EN_SR | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DFI_LP_WAKEUP_PD[3:0] | DFI_LP_EN_PD | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bits 28:24 – DFI_TLP_RESP[4:0]
Setting in DFI clock cycles for DFI's tlp_resp time.
Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Saving modes.
Refer to PHY databook for recommended values
Unit: DFI clock cycles.
Programming Mode: Static
Bits 23:20 – DFI_LP_WAKEUP_DPD[3:0]
Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered.
Determines the DFI's tlp_wakeup time:
- 0x0 - 16 cycles
- 0x1 - 32 cycles
- 0x2 - 64 cycles
- 0x3 - 128 cycles
- 0x4 - 256 cycles
- 0x5 - 512 cycles
- 0x6 - 1024 cycles
- 0x7 - 2048 cycles
- 0x8 - 4096 cycles
- 0x9 - 8192 cycles
- 0xA - 16384 cycles
- 0xB - 32768 cycles
- 0xC - 65536 cycles
- 0xD - 131072 cycles
- 0xE - 262144 cycles
- 0xF - Unlimited
This is only present for designs supporting LPDDR2/LPDDR3 devices.
Unit: DFI clock cycles.
Programming Mode: Static
Bit 16 – DFI_LP_EN_DPD
Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit.
This is only present for designs supporting LPDDR2/LPDDR3 devices.
Programming Mode: Static
| Value | Description |
|---|---|
| 0 | Disabled |
| 1 | Enabled |
Bits 15:12 – DFI_LP_WAKEUP_SR[3:0]
Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Self Refresh mode is entered.
Determines the DFI's tlp_wakeup time:
- 0x0 - 16 cycles
- 0x1 - 32 cycles
- 0x2 - 64 cycles
- 0x3 - 128 cycles
- 0x4 - 256 cycles
- 0x5 - 512 cycles
- 0x6 - 1024 cycles
- 0x7 - 2048 cycles
- 0x8 - 4096 cycles
- 0x9 - 8192 cycles
- 0xA - 16384 cycles
- 0xB - 32768 cycles
- 0xC - 65536 cycles
- 0xD - 131072 cycles
- 0xE - 262144 cycles
- 0xF - Unlimited
Unit: DFI clock cycles.
Programming Mode: Static
Bit 8 – DFI_LP_EN_SR
Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit.
Programming Mode: Static
| Value | Description |
|---|---|
| 0 | Disabled |
| 1 | Enabled |
Bits 7:4 – DFI_LP_WAKEUP_PD[3:0]
Value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered.
Determines the DFI's tlp_wakeup time:
- 0x0 - 16 cycles
- 0x1 - 32 cycles
- 0x2 - 64 cycles
- 0x3 - 128 cycles
- 0x4 - 256 cycles
- 0x5 - 512 cycles
- 0x6 - 1024 cycles
- 0x7 - 2048 cycles
- 0x8 - 4096 cycles
- 0x9 - 8192 cycles
- 0xA - 16384 cycles
- 0xB - 32768 cycles
- 0xC - 65536 cycles
- 0xD - 131072 cycles
- 0xE - 262144 cycles
- 0xF - Unlimited
Unit: DFI clock cycles.
Programming Mode: Static
Bit 0 – DFI_LP_EN_PD
Enables DFI Low Power interface handshaking during Power Down Entry/Exit.
Programming Mode: Static
| Value | Description |
|---|---|
| 0 | Disabled |
| 1 | Enabled |