17.31 UDDRC SDRAM Timing Register 7
| Name: | UDDRC_DRAMTMG7 |
| Offset: | 0x11C |
| Reset: | 0x00000202 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| T_CKPDE[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 1 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| T_CKPDX[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 1 | 0 | |||||
Bits 11:8 – T_CKPDE[3:0]
This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE.
Recommended settings:
- LPDDR2: 2
- LPDDR3: 2
When using DDR2/3 SDRAM, this register should be set to the same value as DRAMTMG5.t_cksre.
When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer.
This is only present for designs supporting LPDDR2/LPDDR3 devices.
Unit: DFI clock cycles.
Programming Mode: Quasi-dynamic Group 2, Group 4
Bits 3:0 – T_CKPDX[3:0]
This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX.
Recommended settings:
- LPDDR2: 2
- LPDDR3: 2
When using DDR2/3 SDRAM, this register should be set to the same value as DRAMTMG5.t_cksrx.
When the controller is operating in 1:2 frequency ratio mode, program this to recommended value divided by two and round it up to next integer.
This is only present for designs supporting LPDDR2/LPDDR3 devices.
Unit: DFI clock cycles.
Programming Mode: Quasi-dynamic Group 2, Group 4