17.57 UDDRC ODT Configuration Register
| Name: | UDDRC_ODTCFG |
| Offset: | 0x240 |
| Reset: | 0x04000400 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WR_ODT_HOLD[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 1 | 0 | 0 | |||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| WR_ODT_DELAY[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RD_ODT_HOLD[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 1 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RD_ODT_DELAY[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
Bits 27:24 – WR_ODT_HOLD[3:0]
DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2.
Recommended values:
DDR2:
- BL8: 0x5 (DDR2-400/533/667), 0x6 (DDR2-800), 0x7 (DDR2-1066)
- BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066)
DDR3:
- BL8: 0x6
WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble)
CRC_MODE = 0 (not CRC mode), 1 (CRC mode)
LPDDR3:
- BL8: 7 + RU(tODTon(max)/tCK)
Unit: DFI PHY clock cycles.
Programming Mode: Quasi-dynamic Group 1, Group 4
Bits 20:16 – WR_ODT_DELAY[4:0]
The delay, in DFI PHY clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the UDDRC.
Recommended values:
DDR2:
- CWL + AL - 3 (DDR2-400/533/667), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066)
If (CWL + AL - 3 < 0), UDDRC does not support ODT for write operation.
DDR3:
- 0x0
LPDDR3:
- WL - 1 - RU(tODTon(max)/tCK))
Unit: DFI PHY clock cycles.
Programming Mode: Quasi-dynamic Group 1, Group 4
Bits 11:8 – RD_ODT_HOLD[3:0]
DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2.
Recommended values:
DDR2:
- BL8: 0x6 (not DDR2-1066), 0x7 (DDR2-1066)
- BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066)
DDR3:
- BL8 - 0x6
LPDDR3:
- BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tCK)
Unit: DFI PHY clock cycles.
Programming Mode: Quasi-dynamic Group 1, Group 4
Bits 6:2 – RD_ODT_DELAY[4:0]
The delay, in DFI PHY clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the UDDRC.
Recommended values:
DDR2:
- CL + AL - 4 (not DDR2-1066), CL + AL - 5 (DDR2-1066)
If (CL + AL - 4 < 0), UDDRC does not support ODT for read operation.
DDR3:
- CL - CWL
LPDDR3:
- RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)
Unit: DFI PHY clock cycles.
Programming Mode: Quasi-dynamic Group 1, Group 4