17.59 UDDRC Scheduler Control Register 0
| Name: | UDDRC_SCHED |
| Offset: | 0x250 |
| Reset: | 0x00001005 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RDWR_IDLE_GAP[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| GO2CRITICAL_HYSTERESIS[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LPR_NUM_ENTRIES[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 1 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PAGECLOSE | PREFER_WRITE | FORCE_LOW_PRI_N | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 1 | 0 | 1 |
Bits 30:24 – RDWR_IDLE_GAP[6:0]
When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is non-empty.
The read transaction store (both high and low priority) is the default preferred transaction store and the write transaction store is the alternative store.
When prefer write over read is set this is reversed.
0x0 is a legal value for this register. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true.
For performance only.
Unit: DFI clock cycles.
Programming Mode: Static
Bits 23:16 – GO2CRITICAL_HYSTERESIS[7:0] UNUSED
Programming Mode: Static
Bits 12:8 – LPR_NUM_ENTRIES[4:0]
Number of entries in the low priority transaction store is this value + 1.
(2 - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high priority transaction store.
Setting this to maximum value allocates all entries to low priority transaction store.
Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high priority transaction store.
Programming Mode: Static
Bit 2 – PAGECLOSE
If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this register set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some cases where there is a mode switch between Write and Read or between LPR and HPR.
If false, the bank remains open until there is a need to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open page policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre).
The pageclose feature provids a midway between Open and Close page policies.
For performance only.
Programming Mode: Quasi-dynamic Group 3
Bit 1 – PREFER_WRITE
If set then the bank selector prefers writes over reads.
For debug only.
Programming Mode: Static
Bit 0 – FORCE_LOW_PRI_N
Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Priority Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write side, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming transactions to low priority implicitly turns off Bypass path for read commands.
For performance only.
Programming Mode: Static