17.33 UDDRC SDRAM Timing Register 14
| Name: | UDDRC_DRAMTMG14 |
| Offset: | 0x138 |
| Reset: | 0x000000A0 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| T_XSR[11:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| T_XSR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | |
Bits 11:0 – T_XSR[11:0] tXSR: Exit Self Refresh to any command.
When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value.
The value 0xfff is illegal for this register field.
Unit: DFI clock cycles.
Programming Mode: Quasi-dynamic Group 2, Group 4
Note: Used only for LPDDR2/LPDDR3 mode.