17.1 UDDRC Host Register 0


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
					BURST_RDWR[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	1	0	0


Bit	15	14	13	12	11	10	9	8
	DLL_OFF_MODE		DATA_BUS_WIDTH[1:0]			EN_2T_TIMING_MODE	BURSTCHOP
Access	R/W		R/W	R/W		R/W	R/W
Reset	0		0	0		0	0


Bit	7	6	5	4	3	2	1	0
					LPDDR3	LPDDR2		DDR3
Access					R/W	R/W		R/W
Reset					0	0		1

Bits 19:16 – BURST_RDWR[3:0] SDRAM burst length used

This controls the burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-the-fly mode of DDR3, set this field to 0x0100). Burst length of 2 is not supported.

Burst length of 2 is only supported when the controller is operating in 1:1 frequency mode.

For DDR3 and LPDDR3, this must be set to 0x0100 (BL8).

Programming mode: Static

Value	Description
0001	Reserved
0010	Burst length of 4
0100	Burst length of 8
1000	Burst length of 16 (only supported for LPDDR2)
–	All other values are reserved.

Bit 15 – DLL_OFF_MODE

Set to 1 when the UDDRC and DRAM has to be put in DLL-off mode for low frequency operation.

Set to 0 to put UDDRC and DRAM in DLL-on mode for normal frequency operation.

Programming mode: Quasi-dynamic Group 2

Bits 13:12 – DATA_BUS_WIDTH[1:0]

Selects proportion of DQ bus width that is used by the SDRAM.

Note that half bus width mode is only supported when the SDRAM bus width is a multiple of 16. Bus width refers to DQ bus width.

Programming mode: Static

Value	Description
00	Full DQ bus width to SDRAM
01	Half DQ bus width to SDRAM
10	Quarter DQ bus width to SDRAM
11	Reserved

Bit 10 – EN_2T_TIMING_MODE

If 1, then UDDRC uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command.

2T timing is not supported in the following cases:

in LPDDR2/LPDDR3 mode
in Shared-AC dual channel mode and the register value is don't care.

Programming mode: Static

Bit 9 – BURSTCHOP

When set, enable burst-chop (BC4 or 8 on-the-fly) in DDR3. Burst Chop for Reads is not exercised. Burst Chop for Writes is exercised.

BC4 (fixed) mode is not supported.

Programming mode: Static

Bit 3 – LPDDR3 Select LPDDR3 SDRAM

Present only in designs configured to support LPDDR3.

Programming mode: Static

Value	Description
0	Non-LPDDR3 device in use.
1	LPDDR3 SDRAM device in use.

Bit 2 – LPDDR2 Select LPDDR2 SDRAM

Present only in designs configured to support LPDDR2.

Programming mode: Static

Value	Description
0	Non-LPDDR2 device in use
1	LPDDR2 SDRAM device in use.

Bit 0 – DDR3 Select DDR3 SDRAM

Only present in designs that support DDR3.

Programming mode: Static

Value	Description
0	Non-DDR3 SDRAM device in use
1	DDR3 SDRAM device in use

Name:	UDDRC_MSTR
Offset:	0x000
Reset:	0x00040001
Property:	Read/Write