17.65 UDDRC Debug Register 1
| Name: | UDDRC_DBG1 |
| Offset: | 0x304 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIS_HIF | DIS_DQ | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 1 – DIS_HIF
When 1, UDDRC asserts the HIF command signal hif_cmd_stall. UDDRC will ignore the hif_cmd_valid and all other associated request signals.
This bit is intended to be switched on-the-fly.
Programming Mode: Dynamic
Bit 0 – DIS_DQ
When 1, UDDRC will not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted.
This bit may be used to prevent reads or writes being issued by the UDDRC, which makes it safe to modify certain register fields associated with reads and writes. After setting this bit, it is strongly recommended to poll DBGCAM.wr_data_pipeline_empty and DBGCAM.rd_data_pipeline_empty, before making changes to any registers which affect reads and writes. This will ensure that the relevant logic in the DDRC is idle.
This bit is intended to be switched on-the-fly.
Programming Mode: Dynamic