17.70 UDDRC Software Register Programming Control Status
Name:
UDDRC_SWSTAT
Offset:
0x324
Reset:
0x00000001
Property:
Read-only
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
SW_DONE_ACK
Access
R
Reset
1
Bit 0 – SW_DONE_ACK Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination clock domains.
Programming Mode: Static
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