17.75 UDDRC Port Common Configuration Register
| Name: | UDDRC_PCCFG |
| Offset: | 0x400 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BL_EXP_MODE | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PAGEMATCH_LIMIT | GO2CRITICAL_EN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 8 – BL_EXP_MODE
Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using the memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit.
This applies to both reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect.
Functionality is also not supported if Data Channel Interleave is enabled
Programming Mode: Static
Bit 4 – PAGEMATCH_LIMIT
Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same page DDRC transactions.
Programming Mode: Static
Bit 0 – GO2CRITICAL_EN
If set to 1 (enabled), sets the co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent, arurgent) coming from the AXI host. If set to 0 (disabled), the co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.
For uPCTL2, this register field must be set to 0
Programming Mode: Static