17.38 UDDRC ZQ Status Register
| Name: | UDDRC_ZQSTAT |
| Offset: | 0x18C |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ZQ_RESET_BUSY | |||||||||
| Access | R | ||||||||
| Reset | 0 |
Bit 0 – ZQ_RESET_BUSY SoC core may initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the UDDRC accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period is over. It is recommended not to perform ZQ Reset commands when this signal is high.
Programming Mode: Dynamic
| Value | Description |
|---|---|
| 0 | Indicates that the SoC core can initiate a ZQ Reset operation. |
| 1 | Indicates that ZQ Reset operation is in progress. |