17.19 UDDRC SDRAM Initialization Register 2
| Name: | UDDRC_INIT2 |
| Offset: | 0x0D8 |
| Reset: | 0x00000D05 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| IDLE_AFTER_RESET_X32[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MIN_STABLE_CLOCK_X1[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 1 | 0 | 1 | |||||
Bits 15:8 – IDLE_AFTER_RESET_X32[7:0] Idle time after the reset command, tINIT4
When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value.
Unit: Multiples of 32 DFI clock cycles.
Programming mode: Static
Bits 3:0 – MIN_STABLE_CLOCK_X1[3:0] Time to wait after the first CKE high, tINIT2
LPDDR2/LPDDR3 typically requires 5 x tCK delay.
When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value.
Unit: DFI clock cycles.
Programming mode: Static