17.20 UDDRC SDRAM Initialization Register 3
| Name: | UDDRC_INIT3 |
| Offset: | 0x0DC |
| Reset: | 0x00000510 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| MR[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| MR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| EMR[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EMR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | |
Bits 31:16 – MR[15:0]
DDR3: value loaded into MR0 register.
LPDDR2/LPDDR3: value to write to MR1 register
Programming mode: Quasi-dynamic Group 1, Group 4
Bits 15:0 – EMR[15:0]
DDR3: value to write to MR1 register. Set bit 7 to 0.
LPDDR2/LPDDR3: value to write to MR2 register
Programming mode: Quasi-dynamic Group 4