17.64 UDDRC Debug Register 0
| Name: | UDDRC_DBG0 |
| Offset: | 0x300 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DIS_COLLISION_PAGE_OPT | DIS_ACT_BYPASS | DIS_RD_BYPASS | DIS_WC | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 4 – DIS_COLLISION_PAGE_OPT
When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.dis_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word).
For debug only.
Programming Mode: Static
Bit 2 – DIS_ACT_BYPASS
Only present in designs supporting activate bypass.
When 1, disable bypass path for high priority read activates
For debug only.
Programming Mode: Static
Bit 1 – DIS_RD_BYPASS
Only present in designs supporting read bypass.
When 1, disable bypass path for high priority read page hits.
For debug only.
Programming Mode: Static
Bit 0 – DIS_WC
When 1, disable write combine.
For debug only
Programming Mode: Static