17.18 UDDRC SDRAM Initialization Register 1

Name:	UDDRC_INIT1
Offset:	0x0D4
Reset:	0x00000000
Property:	Read/Write


Bit	31	30	29	28	27	26	25	24
								DRAM_RSTN_X1024[8]
Access								R/W
Reset								0


Bit	23	22	21	20	19	18	17	16
	DRAM_RSTN_X1024[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
					PRE_OCD_X32[3:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0

Bits 24:16 – DRAM_RSTN_X1024[8:0]

Number of cycles to assert SDRAM reset signal during init sequence.

This is only present for designs supporting DDR3 devices. For use with a DDR PHY, this should be set to a minimum of 1.

When the controller is operating in 1:2 frequency ratio mode, program this to JEDEC spec value divided by 2, and round it up to the next integer value.

Unit: Multiples of 1024 DFI clock cycles.

Programming mode: Static

Bits 3:0 – PRE_OCD_X32[3:0]

Wait period before driving the OCD complete command to SDRAM.

There is no known specific requirement for this; it may be set to zero.

Unit: Multiples of 32 DFI clock cycles.

Programming mode: Static