17.3 UDDRC Mode Register Read/Write Control Register 0


Bit	31	30	29	28	27	26	25	24
	MR_WR
Access	R/W
Reset	0


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	MR_ADDR[3:0]
Access	R/W	R/W	R/W	R/W
Reset	0	0	0	0


Bit	7	6	5	4	3	2	1	0
				MR_RANK				MR_TYPE
Access				R/W				R/W
Reset				1				0

Bit 31 – MR_WR

Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the UDDRC automatically clears this bit.

The other register fields of this register must be written in a separate APB transaction, before setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep Power-down or MPSM operating modes.

Programming mode: Dynamic

Bits 15:12 – MR_ADDR[3:0] Address of the Mode register that is to be written to.

Don't Care for LPDDR2/LPDDR3 (see UDDRC_MRCTRL1.MR_DATA for mode register addressing in LPDDR2/LPDDR3).

This signal is also used for writing to control words of the register chip on RDIMMs/LRDIMMs. In that case, it corresponds to the bank address bits sent to the RDIMM/LRDIMM.

Programming mode: Dynamic

Value	Description
0000	MR0
0001	MR1
0010	MR2
0011	MR3
0100	MR4
0101	MR5
0110	MR6
0111	MR7

Bit 4 – MR_RANK

Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1. However, for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring, it may be necessary to access ranks individually.

Examples (assume UDDRC is configured for 4 ranks):

Programming mode: Dynamic

Value	Description
0x1	Select rank 0 only
0x2	Select rank 1 only
0x5	Select ranks 0 and 2
0xA	Select ranks 1 and 3
0xF	Select ranks 0, 1, 2 and 3

Bit 0 – MR_TYPE

Indicates whether the Mode register operation is read or write. Only used for LPDDR2/LPDDR3.

Programming mode: Dynamic

Value	Description
0	Write
1	Read

Name:	UDDRC_MRCTRL0
Offset:	0x010
Reset:	0x00000010
Property:	R/W