17.25 UDDRC SDRAM Timing Register 1
| Name: | UDDRC_DRAMTMG1 |
| Offset: | 0x104 |
| Reset: | 0x00080414 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| T_XP[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 1 | 0 | 0 | 0 | ||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| RD2PRE[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 1 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| T_RC[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 1 | 0 | 1 | 0 | 0 | ||
Bits 20:16 – T_XP[4:0]
tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exit is selected in MR0[12].
When the controller is operating in 1:2 frequency ratio mode, program this to (tXP/2) and round it up to the next integer value.
Units: DFI clock cycles.
Programming Mode: Quasi-dynamic Group 2, Group 4
Bits 13:8 – RD2PRE[5:0]
tRTP: Minimum time from read to precharge of same bank.
- DDR2: tAL + BL/2 + max(tRTP, 2) - 2
- DDR3: tAL + max (tRTP, 4)
- LPDDR2: Depends on if it's LPDDR2-S2 or LPDDR2-S4:
LPDDR2-S2: BL/2 + tRTP - 1.
LPDDR2-S4: BL/2 + max(tRTP,2) - 2.
- LPDDR3: BL/2 + max(tRTP,4) - 4
When the controller is operating in 1:2 mode, 1T mode, divide the above value by 2. No rounding up.
When the controller is operating in 1:2 mode or 2T mode, divide the above value by 2 and round it up to the next integer value.
Unit: DFI clock cycles.
Programming Mode: Quasi-dynamic Group 1, Group 2, Group 4
Bits 6:0 – T_RC[6:0]
tRC: Minimum time between activates to same bank.
When the controller is operating in 1:2 frequency ratio mode, program this to (tRC/2) and round up to next integer value.
Unit: DFI clock cycles.
Programming Mode: Quasi-dynamic Group 2, Group 4