17.37 UDDRC ZQ Control Register 2
| Name: | UDDRC_ZQCTL2 |
| Offset: | 0x188 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ZQ_RESET | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bit 0 – ZQ_RESET
Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete, the UDDRC automatically clears this bit. It is recommended NOT to set this register bit if in Init, in Self-Refresh or Deep power-down operating modes.
For Self-Refresh or SR-Powerdown it will be scheduled after SR has been exited.
For Deep power down, it will not be scheduled, although ZQSTAT.zq_reset_busy will be de-asserted.
This is only present for designs supporting LPDDR2/LPDDR3 devices.
Programming Mode: Dynamic