17.71 UDDRC AXI Poison Configuration Register. Common for all AXI ports
| Name: | UDDRC_POISONCFG |
| Offset: | 0x36C |
| Reset: | 0x00110011 |
| Property: | R/W |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RD_POISON_INTR_CLR | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| RD_POISON_INTR_EN | RD_POISON_SLVERR_EN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 1 | 1 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| WR_POISON_INTR_CLR | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| WR_POISON_INTR_EN | WR_POISON_SLVERR_EN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 1 | 1 |
Bit 24 – RD_POISON_INTR_CLR Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. UDDRC automatically clears this bit.
Programming Mode: Dynamic
Bit 20 – RD_POISON_INTR_EN If set to 1, enables interrupts for read transaction poisoning
Programming Mode: Dynamic
Bit 16 – RD_POISON_SLVERR_EN If set to 1, enables SLVERR response for read transaction poisoning
Programming Mode: Dynamic
Bit 8 – WR_POISON_INTR_CLR Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to core logic and clear the interrupts. UDDRC automatically clears this bit.
Programming Mode: Dynamic
Bit 4 – WR_POISON_INTR_EN If set to 1, enables interrupts for write transaction poisoning
Programming Mode: Dynamic
Bit 0 – WR_POISON_SLVERR_EN If set to 1, enables SLVERR response for write transaction poisoning
Programming Mode: Dynamic