17.8 UDDRC Temperature Derate Control Register
| Name: | UDDRC_DERATECTL |
| Offset: | 0x02C |
| Reset: | 0x00000001 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DERATE_TEMP_LIMIT_INTR_FORCE | DERATE_TEMP_LIMIT_INTR_CLR | DERATE_TEMP_LIMIT_INTR_EN | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 1 |
Bit 2 – DERATE_TEMP_LIMIT_INTR_FORCE Interrupt force bit for derate_temp_limit_intr
Setting this register to 1 will cause the derate_temp_limit_intr output pin to be asserted.
At the end of the interrupt force operation, the UDDRC automatically clears this bit.
Programming mode: Dynamic
Bit 1 – DERATE_TEMP_LIMIT_INTR_CLR Interrupt clear bit for derate_temp_limit_intr
At the end of the interrupt clear operation, the UDDRC automatically clears this bit.
Programming mode: Dynamic
Bit 0 – DERATE_TEMP_LIMIT_INTR_EN Interrupt enable bit for derate_temp_limit_intr output pin
Programming mode: Dynamic
| Value | Description |
|---|---|
| 0 | Enabled |
| 1 | Disabled |