17.66 UDDRC CAM Debug Register


Bit	31	30	29	28	27	26	25	24
			WR_DATA_PIPELINE_EMPTY	RD_DATA_PIPELINE_EMPTY		DBG_WR_Q_EMPTY	DBG_RD_Q_EMPTY	DBG_STALL
Access			R	R		R	R	R
Reset			0	0		0	0	0


Bit	23	22	21	20	19	18	17	16
			DBG_W_Q_DEPTH[5:0]
Access			R	R	R	R	R	R
Reset			0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
			DBG_LPR_Q_DEPTH[5:0]
Access			R	R	R	R	R	R
Reset			0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
			DBG_HPR_Q_DEPTH[5:0]
Access			R	R	R	R	R	R
Reset			0	0	0	0	0	0

Bit 29 – WR_DATA_PIPELINE_EMPTY

This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed.

Programming Mode: Dynamic

Bit 28 – RD_DATA_PIPELINE_EMPTY

This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq, to ensure that all remaining commands/data have completed.

Programming Mode: Dynamic

Bit 26 – DBG_WR_Q_EMPTY

When 1, all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose.

An example use-case scenario: When Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time.

For debug only

Programming Mode: Dynamic

Bit 25 – DBG_RD_Q_EMPTY

When 1, all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose.

An example use-case scenario: When Controller enters Self-Refresh using the Low-Power entry sequence, Controller is expected to have executed all the commands in its queues and the write and read data drained. Hence this register should be 1 at that time.

For debug only

Programming Mode: Dynamic