17.67 UDDRC Command Debug Register

Setting this register bit to 1 indicates to the UDDRC to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the UDDRC, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.

Programming Mode: Dynamic

Setting this register bit to 1 indicates to the UDDRC to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the UDDRC, the bit is automatically cleared. This operation can be performed only when ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init, in Self-Refresh or Deep power-down operating modes or Maximum Power Saving Mode.

For Self-Refresh it will be scheduled after SR has been exited.

For Deep power down and Maximum Power Saving Mode, it will not be scheduled, although DBGSTAT.zq_calib_short_busy will be de-asserted.

Programming Mode: Dynamic

Setting this register bit to 1 indicates to the UDDRC to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in UDDRC.

For 3DS configuration, refresh is sent to rank index 0.

This operation can be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-down operating modes or Maximum Power Saving Mode.

Programming Mode: Dynamic