17.24 UDDRC SDRAM Timing Register 0
| Name: | UDDRC_DRAMTMG0 |
| Offset: | 0x100 |
| Reset: | 0x0F101B0F |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| WR2PRE[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 1 | 1 | 1 | 1 | ||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| T_FAW[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 1 | 0 | 0 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| T_RAS_MAX[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 1 | 1 | 0 | 1 | 1 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| T_RAS_MIN[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 1 | 1 | 1 | 1 | |||
Bits 30:24 – WR2PRE[6:0]
Minimum time between write and precharge to same bank.
Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies
where:
- WL = write latency
- BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present.
- tWR = Write recovery time. This comes directly from the SDRAM specification.
Add one extra cycle for LPDDR2/LPDDR3 for this parameter.
When the controller is operating in 1:2 frequency ratio mode, 1T mode, divide the above value by 2. No rounding up.
When the controller is operating in 1:2 frequency ratio mode or 2T mode, divide the above value by 2 and round it up to the next integer value.
Note that, depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency through the LRDIMM.
Unit: DFI clock cycles.
Programming Mode: Quasi-dynamic Group 1, Group 2, Group 4
Bits 21:16 – T_FAW[5:0]
tFAW: Valid only when 8 or more banks (or banks x bank groups) are present.
In 8-bank design, at most 4 banks must be activated in a rolling window of tFAW cycles.
When the controller is operating in 1:2 frequency ratio mode, program this to (tFAW/2) and round up to next integer value.
In a 4-bank design, set this register to 0x1 independent of the 1:1/1:2 frequency mode.
Unit: DFI clock cycles.
Programming Mode: Quasi-dynamic Group 2, Group 4
Bits 14:8 – T_RAS_MAX[6:0]
tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open.
Minimum value of this register is 1. Zero is invalid.
When the controller is operating in 1:1 frequency ratio mode, t_ras_max should be set to RoundDown(tRAS(max)/tCK/1024).
When the controller is operating in 1:2 frequency ratio mode, t_ras_max should be set to RoundDown((RoundDown(tRAS(max)/tCK/1024)-1)/2).
Unit: Multiples of 1024 DFI clock cycles.
Programming Mode: Quasi-dynamic Group 2, Group 4
Bits 5:0 – T_RAS_MIN[5:0]
tRAS(min): Minimum time between activate and precharge to the same bank.
When the controller is operating in 1:2 frequency mode, 1T mode, program this to tRAS(min)/2. No rounding up.
When the controller is operating in 1:2 frequency ratio mode or 2T mode, program this to (tRAS(min)/2) and round it up to the next integer value.
Unit: DFI clock cycles.
Programming Mode: Quasi-dynamic Group 2, Group 4