17.32 UDDRC SDRAM Timing Register 8
| Name: | UDDRC_DRAMTMG8 |
| Offset: | 0x120 |
| Reset: | 0x00004405 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| T_XS_DLL_X32[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 1 | 0 | 0 | 0 | 1 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| T_XS_X32[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 1 | 0 | 1 | ||
Bits 14:8 – T_XS_DLL_X32[6:0] tXSDLL: Exit Self Refresh to commands requiring a locked DLL.
When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value.
Unit: Multiples of 32 DFI clock cycles.
Programming Mode: Quasi-dynamic Group 2, Group 4
Note: Used only for DDR2 and DDR3 SDRAMs.
Bits 6:0 – T_XS_X32[6:0] tXS: Exit Self Refresh to commands not requiring a locked DLL.
When the controller is operating in 1:2 frequency ratio mode, program this to the above value divided by 2 and round up to next integer value.
Unit: Multiples of 32 DFI clock cycles.
Programming Mode: Quasi-dynamic Group 2, Group 4
Note: Used only for DDR2 and DDR3 SDRAMs.