17.26 UDDRC SDRAM Timing Register 2

Time from write command to write data on SDRAM interface. This must be set to WL.

Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust the value of WL to compensate for the extra cycle of latency through the RDIMM/LRDIMM.

When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer.

This register field is not required for DDR2 and DDR3, as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols

For all protocols, in addition to programming this register field, it is necessary to program DFITMG0 and DFITMG1 to control the read and write latencies

Unit: DFI clock cycles.

Programming Mode: Quasi-dynamic Group 1, Group 2, Group 4

Time from read command to read data on SDRAM interface. This must be set to RL.

Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to adjust the value of RL to compensate for the extra cycle of latency through the RDIMM/LRDIMM.

When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer.

This register field is not required for DDR2 and DDR3, as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols

For all protocols, in addition to programming this register field, it is necessary to program DFITMG0 and DFITMG1 to control the read and write latencies

Unit: DFI clock cycles.

Programming Mode: Quasi-dynamic Group 1, Group 2, Group 4

DDR2/3: RL + BL/2 + 2 - WL

LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL

Minimum time from read command to write command. Include time for bus turnaround and all per-bank, per-rank, and global constraints.

Please see the relevant PHY databook for details of what should be included here.

Where:

- WL = write latency

- BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM

- RL = read latency = CAS latency

After PHY has completed training the value programmed may need to be increased. Refer to relevant PHY documentation.

For LPDDR2/LPDDR3, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used.

When the controller is operating in 1:2 frequency ratio mode, divide the value calculated using the above equation by 2, and round it up to next integer.

Note that, depending on the PHY, if using LRDIMM, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency through the LRDIMM.

Unit: DFI clock cycles.

Programming Mode: Quasi-dynamic Group 1, Group 2, Group 4

LPDDR2/3: WL + BL/2 + tWTR + 1

Others: CWL + BL/2 + tWTR

Please see the relevant PHY databook for details of what should be included here.

Where:

- CWL = CAS write latency

- WL = Write latency

- PL = Parity latency

- BL = burst length. This must match the value programmed in the BL bit of the mode register to the SDRAM

- tWTR_L = internal write to read command delay for same bank group. This comes directly from the SDRAM specification.

- tWTR = internal write to read command delay. This comes directly from the SDRAM specification.

After PHY has completed training the value programmed may need to be increased. Refer to relevant PHY documentation.

Add one extra cycle for LPDDR2/LPDDR3 operation.

When the controller is operating in 1:2 mode, divide the value calculated using the above equation by 2, and round it up to next integer.

Unit: DFI clock cycles.

Programming Mode: Quasi-dynamic Group 1, Group 2, Group 4