17.27 UDDRC SDRAM Timing Register 3
| Name: | UDDRC_DRAMTMG3 |
| Offset: | 0x10C |
| Reset: | 0x0050400C |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| T_MRW[9:4] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| T_MRW[3:0] | T_MRD[5:4] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 1 | 0 | 1 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| T_MRD[3:0] | T_MOD[9:8] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 1 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| T_MOD[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | |
Bits 29:20 – T_MRW[9:0]
Time to wait after a mode register write or read (MRW or MRR).
Present only in designs configured to support LPDDR2 or LPDDR3.
LPDDR2 typically requires value of 5.
LPDDR3 typically requires value of 10.
For LPDDR2, this register is used for the time from a MRW/MRR to all other commands.
When the controller is operating in 1:2 frequency ratio mode, program this to the above values divided by 2 and round it up to the next integer value.
For LDPDR3, this register is used for the time from a MRW/MRR to a MRW/MRR.
Unit: DFI clock cycles.
Programming Mode: Quasi-dynamic Group 2, Group 4
Bits 17:12 – T_MRD[5:0]
tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents:
DDR2: Time from MRS to any command
DDR3: Time from MRS to MRS command
LPDDR2: not used
LPDDR3: Time from MRS to non-MRS command.
When the controller is operating in 1:2 frequency ratio mode, program this to (tMRD/2) and round it up to the next integer value.
If CAL mode is enabled (DFITMG1.dfi_t_cmd_lat > 0), tCAL (=DFITMG1.dfi_cmd_lat) should be added to the above calculations.
Unit: DFI clock cycles.
Programming Mode: Quasi-dynamic Group 2, Group 4
Bits 9:0 – T_MOD[9:0]
tMOD: Parameter used only in DDR3. Cycles between load mode command and following non-load mode command.
If CAL mode is enabled (DFITMG1.dfi_t_cmd_lat > 0), tCAL (=DFITMG1.dfi_cmd_lat) should be added to the above calculations.
Set to tMOD if controller is operating in 1:1 frequency ratio mode, or tMOD/2 (rounded up to next integer) if controller is operating in 1:2 frequency ratio mode. Note that if using RDIMM/LRDIMM, depending on the PHY, it may be necessary to adjust the value of this parameter to compensate for the extra cycle of latency applied to mode register writes by the RDIMM/LRDIMM chip.
Also note that if using LRDIMM, the minimum value of this register is tMRD_L2 if controller is operating in 1:1 frequency ratio mode, or tMRD_L2/2 (rounded up to next integer) if controller is operating in 1:2 frequency ratio mode.
Unit: DFI clock cycles.
Programming Mode: Quasi-dynamic Group 2, Group 4