17.39 UDDRC DFI Timing Register 0
| Name: | UDDRC_DFITMG0 |
| Offset: | 0x190 |
| Reset: | 0x07020002 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DFI_T_CTRL_DELAY[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 1 | 1 | 1 | ||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DFI_RDDATA_USE_DFI_PHY_CLK | DFI_T_RDDATA_EN[6:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DFI_WRDATA_USE_DFI_PHY_CLK | DFI_TPHY_WRDATA[5:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DFI_TPHY_WRLAT[5:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 1 | 0 | |||
Bits 28:24 – DFI_T_CTRL_DELAY[4:0]
Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligned, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM/LRDIMM, it is necessary to increment this parameter by RDIMM's/LRDIMM's extra cycle of latency in terms of DFI clock.
Unit: DFI clock cycles.
Programming Mode: Quasi-dynamic Group 4
Bit 23 – DFI_RDDATA_USE_DFI_PHY_CLK
Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values.
Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles:
- 0 in terms of HDR (DFI clock) cycles
- 1 in terms of SDR (DFI PHY clock) cycles
Refer to PHY specification for correct value.
Programming Mode: Static
Bits 22:16 – DFI_T_RDDATA_EN[6:0]
Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal.
Refer to PHY specification for correct value.
This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to use the adjusted value of CL in the calculation of trddata_en. This is to compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM.
Unit: DFI clock cycles or DFI PHY clock cycles, depending on DFITMG0.dfi_rddata_use_dfi_phy_clk.
Programming Mode: Quasi-dynamic Group 1, Group 4
Bit 15 – DFI_WRDATA_USE_DFI_PHY_CLK
Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values.
Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles
Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of HDR (DFI clock) or SDR (DFI PHY clock) cycles
- 0 in terms of HDR (DFI clock) cycles
- 1 in terms of SDR (DFI PHY clock) cycles
Refer to PHY specification for correct value.
Programming Mode: Static
Bits 13:8 – DFI_TPHY_WRDATA[5:0]
Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. Note, max supported value is 8.
Unit: DFI clock cycles or DFI PHY clock cycles, depending on DFITMG0.dfi_wrdata_use_dfi_phy_clk.
Programming Mode: Quasi-dynamic Group 4
Bits 5:0 – DFI_TPHY_WRLAT[5:0] Write latency
Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat.
Refer to PHY specification for correct value. Note that, depending on the PHY, if using RDIMM/LRDIMM, it may be necessary to use the adjusted value of CL in the calculation of tphy_wrlat. This is to compensate for the extra cycle(s) of latency through the RDIMM/LRDIMM.
Unit: DFI clock cycles or DFI PHY clock cycles, depending on DFITMG0.dfi_wrdata_use_dfi_phy_clk.
Programming Mode: Quasi-dynamic Group 1, Group 4