17.9 UDDRC Low Power Control Register

Name: UDDRC_PWRCTL
Offset: 0x030
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
 DIS_CAM_DRAIN_SELFREF SELFREF_SW EN_DFI_DRAM_CLK_DISABLEDEEPPOWERDOWN_ENPOWERDOWN_ENSELFREF_EN 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 7 – DIS_CAM_DRAIN_SELFREF

Indicates whether skipping CAM draining is allowed when entering Self-refresh.

This register field cannot be modified while PWRCTL.selfref_sw=1.

Note: PWRCTL.dis_cam_drain_selfref=1 is unsupported in this release. PWRCTL.dis_cam_drain_selfref=0 is required.

Programming mode: Dynamic

ValueDescription
0 CAMs must be empty before entering SR.
1 CAMs are not emptied before entering SR (unsupported).

Bit 5 – SELFREF_SW

A value of 1 to this register causes system to move to Self-refresh state immediately, as long as it is not in Init or DPD/MPSM operating_mode. This is referred to as software entry/exit to Self-refresh.

Programming mode: Dynamic

ValueDescription
0 Software entry to Self-refresh
1 Software exit from Self-refresh

Bit 3 – EN_DFI_DRAM_CLK_DISABLE

Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM.

If set to 0, dfi_dram_clk_disable is never asserted.

Assertion of dfi_dram_clk_disable is as follows:

  • In DDR2/DDR3, can only be asserted in Self-refresh.
  • In LPDDR2/LPDDR3, can be asserted in the following cases:
    • in Self-refresh
    • in Power-down
    • in Deep Power-down
    • during normal operation (clock stop)

Programming mode: Dynamic

Bit 2 – DEEPPOWERDOWN_EN

When this is 1, UDDRC puts the SDRAM into Deep Power-down mode when the transaction store is empty.

This register must be reset to '0' to bring UDDRC out of Deep Power-down mode. Controller performs automatic SDRAM initialization on deep power-down exit.

Present only in designs configured to support LPDDR2 or LPDDR3. For non-LPDDR2/non-LPDDR3, this register should not be set to 1.

For performance only.

Programming mode: Dynamic

Bit 1 – POWERDOWN_EN

If true then the UDDRC goes into Power-down after a programmable number of cycles "maximum idle clocks before power down" (PWRTMG.powerdown_to_x32).

This register bit may be re-programmed during the course of normal operation.

Programming mode: Dynamic

Bit 0 – SELFREF_EN

If true then the UDDRC puts the SDRAM into Self-refresh after a programmable number of cycles "maximum idle clocks before Self Refresh (PWRTMG.selfref_to_x32)". This register bit may be re-programmed during the course of normal operation.

Programming mode: Dynamic