17.45 UDDRC DFI Miscellaneous Control Register
| Name: | UDDRC_DFIMISC |
| Offset: | 0x1B0 |
| Reset: | 0x00000001 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DFI_FREQUENCY[4:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | ||||
| Reset | 0 | 0 | 0 | 0 | 0 | ||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DFI_INIT_START | CTL_IDLE_EN | DFI_INIT_COMPLETE_EN | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 1 |
Bits 12:8 – DFI_FREQUENCY[4:0] Indicates the operating frequency of the system
The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY.
Programming Mode: Quasi-dynamic Group 1
Bit 5 – DFI_INIT_START PHY init start request signal
When asserted, triggers the PHY init start request.
Programming Mode: Quasi-dynamic Group 3
Bit 4 – CTL_IDLE_EN Enables support of ctl_idle signal.
Programming Mode: Static
Bit 0 – DFI_INIT_COMPLETE_EN PHY initialization complete enable signal.
When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisation
Programming Mode: Quasi-dynamic Group 3