17.13 UDDRC Refresh Control Register 3

Name: UDDRC_RFSHCTL3
Offset: 0x060
Reset: 0x00000000
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
          
Access  
Reset  
Bit 76543210 
       REFRESH_UPDATE_LEVELDIS_AUTO_REFRESH 
Access R/WR/W 
Reset 00 

Bit 1 – REFRESH_UPDATE_LEVEL

Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated.

refresh_update_level must not be toggled when the DDRC is in reset (core_ddrc_rstn = 0).

The refresh register(s) are automatically updated when exiting reset.

Programming mode: Dynamic

Bit 0 – DIS_AUTO_REFRESH

When '1', disable Auto-refresh generated by the UDDRC. When Auto-refresh is disabled, the SoC core must generate refreshes using the registers DBGCMD.rankn_refresh.

When dis_auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the UDDRC.

This register field is changeable on the fly.

Programming mode: Dynamic - Refresh Related